FinFET devices are promising candidates for future technology nodes of silicon device technologies such as complementary metal-oxide-semiconductor (CMOS), because they offer a very good channel control via the gate electrode. In some known devices the gate electrode is wrapped around a conducting fin-shaped semiconductor layer, allowing a volume control of the conducting channel in the fin-shaped semiconductor layer. Moreover, FinFETs can easily be fabricated starting from a semiconductor on insulator (SOI) substrate.
Two independently addressable gate electrodes are a very interesting option to achieve an ultimate threshold adjustment, e.g., for applications profiting from multiple threshold voltages Vt. Another advantage of independently addressable gate electrodes is that a shift of the gate work function can be compensated, which opens a wide choice of gate materials. The separation of the gate electrode into two independent gate electrodes on each side of the fin is feasible by deposition of a dielectric layer and a subsequent chemical-mechanical polishing (CMP) step, by or by a self-planarising deposition (spin-on techniques) with an isotropic etch back, as described in US 2005/0124120 A1. However, both CMP and self-planarising deposition solutions are difficult to use in the front end processing, i.e., in the fabrication of the transistor structures on a wafer. For the result of these steps depends strongly on the device density and thus on the layout of the circuits to be fabricated on the respective wafer. This reduces the device yield and affects the performance and reliability of circuits containing such FinFET structures.